The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to techniques which are effective when applied to a semiconductor integrated circuit device (bipolar-CMOS LSI) wherein bipolar transistors and MISFETs coexist on an identical substrate.
Heretofore, in case of manufacturing a bipolar-CMOS LSI in which bipolar transistors and complementary MISFETs are formed on an identical substrate, the bipolar transistors have been formed by the simplest possible process through the utilization of CMOS technology in order to avoid the complication of a process for the manufacture.
The bipolar-CMOS LSI is discussed in, for example, "IEDM 1985, Technical Digest," pp 423-426. A method of manufacturing this bipolar-CMOS LSI is as follows: After an n.sup.+ -type buried layer and a p.sup.+ -type buried layer have been formed in a p.sup.- -type semiconductor substrate, an epitaxial layer is formed on the semiconductor substrate. Subsequently, an n-well and a p-well are respectively formed in the epitaxial layer so as to correspond to the n.sup.+ -type and p.sup.+ -type buried layers. Next, a field insulator film is formed on the selected areas of the surface of the epitaxial layer, whereupon an insulator film is formed on the surfaces of active regions enclosed with the field insulator film. At the next step, the gate electrodes of MISFETs are formed of a first-layer polycrystalline silicon film, whereupon the intrinsic base region of each bipolar transistor is formed by ion implantation. Subsequently, the source regions and drain regions of the n-channel and p-channel MISFETs are formed by ion implantation. The n-channel and p-channel MISFETs are usually put into so-called LDD (Lightly Doped Drain) structures in order to prevent their characteristics from varying due to hot electrons (hot carriers). Accordingly, the source region and drain region are formed in such a way that ion implantation at a low impurity concentration is first carried out using the gate electrode as a mask, that a side wall made of an insulator is subsequently formed on the side surface of the gate electrode, and that ion implantation at a high impurity concentration is thereafter carried out using the side wall as a mask. At the ion implantation steps for forming the source region and drain region of the p-channel MISFET, the graft base region of the bipolar transistor is also formed using a predetermined mask.
Subsequently, part of the insulator film formed on the active region is removed by etching, followed by the formation of a second-layer polycrystalline silicon film on the whole surface of the active region. Subsequently, this polycrystalline silicon film is doped with arsenic by way of example, whereupon the resultant polycrystalline silicon film is patterned to leave only a part corresponding to an emitter region to-be-formed. Next, the semiconductor body in this state is annealed, whereby the arsenic in the polycrystalline silicon film is diffused into the epitaxial layer so as to form the emitter region within the intrinsic base region. The polycrystalline silicon film on the emitter region is left intact, and is used as an emitter electrode. At the next step, an insulator film for passivation is formed on the whole surface of the resultant semiconductor body and is provided with contact holes, whereupon an aluminum film is formed on the whole surface. Subsequently, the aluminum film is patterned to form aluminum electrodes for the emitter, base and collector of the bipolar transistor and aluminum electrodes for the source regions and drain regions of the MISFETs.
In order to raise the operating speed of the bipolar transistor in the bipolar-CMOS LSI, the junction depths of the emitter region and base region need to be reduced. However, when the junction depth of the base region is reduced, there arises the problem that the base resistance of the transistor increases. This is ascribable to such facts that the sheet resistance of the intrinsic base region increases, and that the spacing between the emitter region and the graft base region cannot be narrowed because allowance needs to be made for mask registration.
Meanwhile, as discussed in, for example, "IEDM 1985, Technical Digest," pp. 34-37, in the field of ultrahigh-speed bipolar LSIs, the operating speed of the bipolar transistor is raised by adopting self-alignment technology in order to solve the aforementioned problem. In the bipolar transistor employing the self-alignment technology, a base lead-out electrode made of a p.sup.+ -type polycrystalline silicon film is connected to a graft base region which is formed by the diffusion of a p-type impurity from this base lead-out electrode. An insulator film is formed on the side surface and upper surface of the base lead-out electrode, and a polycrystalline silicon emitter electrode made of an n.sup.+ -type polycrystalline silicon film is formed through this insulator film. An emitter region is formed by the diffusion of an n-type impurity from the polycrystalline silicon emitter electrode. In this case, the base lead-out electrode and the polycrystalline silicon emitter electrode are structurally isolated in self-alignment fashion by the insulator film. Therefore, the spacing between the emitter region and the graft base region can be sufficiently narrowed, so that reduction in the base resistance can be achieved.